`timescale 1ns / 1ps
`include "param.v"

module SEXT(
    input wire [24:0]  din,
    input wire [2:0] sext_op,

    output reg [31:0] ext
    );

 wire sgn = din[24];
    always @(*) begin
    case (sext_op)
        3'b000: begin
            if (sgn == 1'b1)
                ext = {20'hFFFFF, din[24:13]};
            else
                ext = {20'b0, din[24:13]};
        end
        3'b001: ext = {27'b0, din[17:13]};
        3'b010: begin
            if (sgn == 1'b1)
                ext = {20'hFFFFF, din[24:18], din[4:0]};
            else
                ext = {20'b0, din[24:18], din[4:0]};
        end
        3'b011: ext = {din[24:5], 12'b0};
        3'b100: begin
            if (sgn == 1'b1)
                ext = {19'h7FFFF, din[24], din[0], din[23:18], din[4:1], 1'b0};
            else
                ext = {19'b0, din[24], din[0], din[23:18], din[4:1], 1'b0};
        end
        3'b101: begin
            if (sgn == 1'b1)
                ext = {11'h7FF, din[24], din[12:5], din[13], din[23:14], 1'b0};
            else
                ext = {11'b0, din[24], din[12:5], din[13], din[23:14], 1'b0};
        end
        3'b110: ext = {din[24:5], 12'b0};
        default: ext = 32'b0;
    endcase
end



endmodule